← Ch.4
von Neumann CPU
Interact
Tour
Buses
FDE
Performance
Interrupts
CPU
address bus
data bus
control bus
Address bus
Data bus
Control bus
Internal link
memory address
register (MAR)
program counter
(PC)
memory data
register (MDR)
status register
(SR)
system
clock
CONTROL UNIT (CU)
current instruction
register (CIR)
ARITHMETIC AND
LOGIC UNIT (ALU)
accumulator
(ACC)
index register (IX)
IAS (RAM)
1111 0000
0111 0010
1111 0001
0101 1011
1111 0010
1101 1101
1111 0011
0111 1011
← Step
Step →
Reset
